1. Field of the Invention
This invention relates to an information processing system and more particularly to an information processing system with a virtual addressing system capable of paging.
2. Description of the Prior Art
A virtual memory is used to make available for the user a larger amount of additional memory space than the actual capacity of a main memory. The user can write a program with a virtual address, however, the virtual address is usually transferred to a channel after it is translated into a real address at an input and output control portion of an operating system when it is input or output. Namely, in a computer system using the virtual memory, a central processing unit (CPU) typically has a hardware configuration including a so-called dynamic address translator (DAT) architecture to change the virtual memory space selected by the user into the real memory space. There are a few cases where the hardware architecture is applied even to the channel which controls the input and output operations. If the channel does not have the DAT, it is necessary for the operating system to convert a channel program written using virtual addressing to a channel program written using real addressing. If there is a branch command in the channel program, or if memory area in virtual address space for input and/or output data is more than a few pages, however, the translation operation will be very complicated. For simplifying the translation operation, there is an improved system which is designed to enable the use of an indirect address scheme at the channel. However, the disadvantage of this system is that the operating system has to trace the channel program and translate it into the real address, and the number of dynamic steps for the operating system would be too great.
FIG. 1 shows a block diagram of a prior art information processing system. In FIG. 1 there are shown the main memory 10, a main memory controller 11, a central processing unit (CPU) 12, and input/output controllers (IOC) 14 and 15. The CPU 12 and the IOC's 14 and 15 are respectively connected to the main memory controller (MMC) 11 through a common bus 17. The MMC is designed to access the main memory 10. In the system, the main memory 10 includes a plurality of main memory modules MM0, MM1, MM2 and MM3. The IOC 14 connects the magnetic disk apparatus MK and the other IOC 15 connects a card reader R and a line printer LP through an input and output bus to the MMC 11. The CPU 12 includes a dynamic address translator (DAT) 13. Therefore, the virtual address given by the program is translated by the DAT 13 and is sent to the main memory controller 11 through the common bus 17. The associative address given by the channel program is translated into the actual address by a method of software, and such real address as a part of the so-called input/output command is then transferred to the IOCs 4 and 15. In this address translation method, the CPU bears too many loads to operate the system efficiently. However, there is a system which improves upon the above disadvantages of the input and output channel as shown in FIG. 1, wherein the IOCs 14 and 15 also have a DAT. For example, the IBM 4341 processor is explained in the publication, "A guide to the IBM 4341 Processor (GC20-1877)" published by IBM corporation. However, the system still requires the double DAT architecture, one for the CPU and one for the IOC, so that the efficiency of the system is lower.